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ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 1 of 11 1 - 888 - 824 - 4184 features form, fit, and function compatible with the intel a 82510 packaging options available: 28 pin plastic or ceramic dip, 28 pin plastic leaded chip carrier, 28 pin ceramic leadless chip carrier asynchronous serial channel operation separate transmit and receive fifos with programmable threshold programmable baud rate generators up to 288k baud special protocol features - control character recognition - auto echo and loopback modes - 9 - bit protocol support - 5 to 9 bit character format the ia82510 is a "plug - and - play" drop - in replacement for the original ic. innov asic produces replacement ics using its miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" whi le ensuring they are compatible with the original ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocumented features" are d uplicated. this data sheet documents all necessary engineering information about the ia82510 including functional and i/o descriptions, electrical characteristics, and applicable timing. package pinout (6) txd (1) d4 (2) d5 (3) d6 (4) d7 (5) int (7) vss (8) x2 or out2n (9) x1 or clk (10) sclk or rin (11) dsrn or ta or out0n (12) dcdn or iclk or out1n (13) rxd (14) ctsn 28 pin dip ia82510 (28) d3 (27) d2 (26) d1 (25) d0 (24) a2 (23) a1 (22) a0 (21) vdd (20) rdn (19) wrn (18) csn (17) reset (16) rtsn (15) dtrn or tb 28 pin lcc ia82510 (6) txd (5) int (7) vss (8) x2 or out2n (9) x1 or clk (10) sclk or rin (11) dsrn or ta or out0n (25) d0 (24) a2 (23) a1 (22) a0 (21) vdd (20) rdn (19) wrn (4) d7 (3) d6 (2) d5 (1) d4 (28) d3 (27) d2 (26) d1 (18) csn (17) reset (16) rtsn (15) dtrn or tb (14) ctsn (13) rxd (12) dcdn or iclk or out1n
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 2 of 11 1 - 888 - 824 - 4184 description the ia82510 is an asynchronous serial controller tha t provides a cpu interface to one transmit and one receive channel. it is form, fit, and function compatible with the intel 82510. configuration registers are used to control the serial channel, interrupts, and modes of operation. the cpu controls this d evice via address and data lines with read/write control. the cpu also uses this interface to read and write data to receive and transmit data through the serial channel. fifos and various serial modes can be used to help off - load the cpu from transmitti ng and receiving data. an interrupt line provides an indication to the cpu that the device requires servicing. the device can be configured for 8250a/16450 compatibility. functional block diagram ia82510 bus interface (reset logic, registers, interrupt generation, config., status, rxdata txdata timing (baud rate generators a & b, clocking pin configuration receiver transmitter modem txd rxd x2 or out2n sclk or rin x1 or clk rtsn ctsn dsrn or ta or out0n dcdn or iclk or out1n dtrn or tb a(2:0) d(7:0) rdn wrn csn int reset
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 3 of 11 1 - 888 - 824 - 4184 functional overview transmitter the transmit functio n consists of a 4 11 bit fifo, and a transmit engine. the 4 11 fifo is configurable as any depth between one and four words inclusive. the transmit engine is responsible for reading the data out of the fifo and placing it in the proper order on the tx d pin. the transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. transmit communication parameters that can be programmed include: parity modes stop bits character length fifo dept h clocking options rts and cts modes see the register description for more details. receiver the receiver function consists of a 4 11 configurable fifo and a receive engine. the receive engine is responsible for sampling the data on the rxd input pin, formatting the data, and placing the data in the fifo. the receive engine is highly configurable with parameters that include: parity modes stop bits character length fifo depth clocking options address matching options control character detection rts and cts modes see the register description for more details. bus interface the bus interface is a simple interface that allows a micro - processor or micro - controller to read and write the ia82510 registers. it consists of the following i/o lines: a0, a1, a2 : 3 bit address d0 - d7 : 8 bit data rdn: active low read enable wrn: active low write enable csn: active low chip select int: interrupt output reset: chip reset
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 4 of 11 1 - 888 - 824 - 4184 register description table 1 ? ia82510 register summary register addr bank dlab mode d efault acr0 111 00 x r/w 00000000 acr1 101 10 x r/w 00000000 bacf 001 11 0 r/w 00000100 bah 001 00 1 r/w 00000000 bal 000 00 1 r/w 00000010 bank 010 x x w 00000000 bbcf 011 11 x r/w 10000100 bbh 001 11 1 r/w 00000000 bbl 000 11 1 r/w 00000101 clc f 000 11 0 r/w 00000000 flr 100 01 x r 00000000 fmd 001 10 x r/w 00000000 ger 001 00 0 r/w 00000000 gir_bank 010 x x r 00000001 gsr 111 01 x r 00010010 icm 111 01 x w n/a imd 100 10 x r/w 00001100 lcr 011 00 x r/w 00000000 lsr 101 00 x r/w 0110000 0 mcr 100 100 00 01 x x r/w w 00000000 mie 101 11 x r/w 00001111 msr 110 110 00 01 x x r/w r 00000000 pmd 100 11 x r/w 11111100 rcm 101 01 x w n/a rie 110 10 x r/w 00011110 rmd 111 10 x r/w 00000000 rst 101 01 x r 00000000 rxdata 000 00 01 0 x r unknown rxf 001 01 x r unknown tcm 110 01 x w n/a tmcr 011 01 x w n/a tmd 011 10 x r/w 00000000 tmie 110 11 x r/w 00000000 tmst 011 01 x r 00110000 txdata 000 00 01 0 x w n/a txf 001 01 x w n/a
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 5 of 11 1 - 888 - 824 - 4184 ac/dc parameters absolute maximum ratings: supply voltage, v dd ???????????.? - 0.3v to +6.0v input voltage, v in ????????????? - 0.3v to v dd +0.3v input pin current, iin???????????.10 ma, 25 c operating temperature range????????.. - 40 c to +85c ambient temperature under bias........................??.. - 40c t o +85c * storage temperature.......................................?........?. - 55c to +150c lead temperature?????????????.+300c, 10 sec. power dissipation..............................................................155 mw, 125c, 25mhz, 15% toggle s tresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. operating the device beyond the conditions indicated in the ?recommended operating conditions? section is not recommended. operation at the ?absolute m aximum ratings? may adversely affect device reliability. * the input and output parametric values in section vii - b, parts 1, 2, and 3, are directly related to ambient temperature and dc supply voltage. a temperature or supply voltage range other than thos e specified in the operating conditions above will affect these values and part performance is not guaranteed by innovasic.
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 6 of 11 1 - 888 - 824 - 4184 dc characteristics symbol parameter notes min max unit v il input low voltage (1) -0.5 0.7 v v ih1 input high voltage-cerdip (1) 2.1 v dd +.07 v v ih2 input high voltage-lcc (2) 2.1 v dd +.07 v v ol output low voltage (2), (8) 0.4 v v oh output high voltage (3), (8) 2.4 v i li input leakage current (4) 1 a i lo 3-state leakage current (5) 1 a i cc power supply current (6) 1.12 ma/mhz i pu strapping pullup resistor (12) -283 -137 a i stby standby supply current (9) 100 a i ohr rtsn, dtrn strapping current (10) 1.92 ma i olr rtsn, dtrn strapping current (11) n/a ma c in input capacitance (7) 5 pf c io i/o capacitance (7) 6 pf c xtal x1, x2 load 6 pf notes: 4. 0< v in < v cc . 5. 0.4v < v out < v cc - 0.4v 7. freq. = 1mhz. 8. does not apply to out2/x2 pin, when configured as crystal oscillator output (x2). 1. does not apply to clk/x1 pin, when configured as crystal oscillator input (x1). 10. applies only during hardware reset for clock configuration options. strapping current for logic high. 11. applies only during hardware reset for clock configuration options. strapping current for logic low 12. inputs (rtsn, dtrn, tb) with pullups tested @ v in = 0.0v v dd = 5.5v 6. v dd = 5.5v, v il = 0.7v (max), v ih = v dd - 0.7v (min), typ. val = 1.12 ma/mhz (not tested), ext. 1x clk, i ol = i oh = 0. 3. @ i oh = 1.92 ma 2. @ i ol = 1.92 ma static idd current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to vdd or vss, configured to draw minimum current. 9. freq. = 1mhz. but, input clock not running.
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 7 of 11 1 - 888 - 824 - 4184 ac characteristics parameter min max notes clk period 54 ns 250 ns divide by two clk period 54 ns 108 ns no divide by clk low time 25 ns clk high time 25 ns clk rise time 10 ns divide by two measured between 0.3 * vdd and 0.7 * vdd clk fall time 10 ns divide by two measured between 0.3 * vdd and 0.7 * vdd clk rise time 15 ns no divide by clk fall time 15 ns no divide by crystal frequency 1 mhz 20 mhz reset width 8 * clock period rts/dtr low setup to reset inactive 6 * clock period rts/dtr low hold after reset inactive clock period ? 20 ns rdn active width 2* clock period + 65 ns address/csn setup time to rdn active 7 ns address/csn hold after rdn inactive 0 ns rdn or wrn inactive to active delay clock period + 15 ns data out float delay after rdn inactive 40 ns wrn active width 2 * clock period + 15 ns address csn setup time to wrn active 7 ns address and csn hold time after wrn 0 ns data in setup time to wrn inactive 90 ns data in hold time after wrn inactive 12 ns sclk period 216 ns 16x clocking mode sclk period 3500 ns 1x clo cking mode rxd setup time to sclk high 250 ns rxd hold time after sclk high 250 ns txd valid after sclk low 170 ns txd delay after rxd 170 ns remote loopback
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 8 of 11 1 - 888 - 824 - 4184 .10 .51 min. r 1.14 / .64 seating plane a1 e .81 / .66 a .53 / .33 d2 / e2 side view packaging information plcc package lead count 28 (in millimeters) symbol mi n max a 4.20 4.57 a1 2.29 3.04 d1 11.43 11.58 d2 9.91 10.92 d3 7.62 bsc e1 11.43 11.58 e2 9.91 10.92 e3 7.62 bsc e 1.27 bsc d 12.32 12.57 e 12.32 12.57 d d1 e e1 bottom view d3 e3 pin 1 identifier & zone 1.22/1.07 2 plcs top view
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 9 of 11 1 - 888 - 824 - 4184 pdip package lead count 28 (in inches) symbol min max a - .200 a1 .015 - b . 015 .020 b1 .050 .070 c .008 .012 d 1.380 1.470 e .580 .610 e1 .520 .560 e .100 typ ea .580 - eb - .686 l .100 min b2 - - s - - ea eb c side view (width) d l a1 a b b1 e side view (length) lead 1 identifier 1 lead count direction e1 e top
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 10 of 11 1 - 888 - 824 - 4184 ordering information the ia82510 is available in two production versions as shown in the tables below. produc tion version 00 order number environment package type ia82510 - cd28m - 00 military 28 lead ceramic dip, 600 mil wide ia82510 - pdw28i - 00 industrial ia82510 - pdw28c - 00 commercial 28 lead plastic dip, 600 mil wide ia82510 - clc28m - 00 military 28 lead ceramic l eaded chip carrier ia82510 - cll28m - 00 military 28 lead ceramic leadless chip carrier ia82510 - plc28i - 00 industrial ia82510 - plc28c - 00 commercial 28 lead plastic leaded chip carrier production version 01 order number environment package type ia82510 - cd 28m - 01 military 28 lead ceramic dip, 600 mil wide ia82510 - pdw28i - 01 industrial ia82510 - pdw28c - 01 commercial 28 lead plastic dip, 600 mil wide ia82510 - clc28m - 01 military 28 lead ceramic leaded chip carrier ia82510 - cll28m - 01 military 28 lead ceramic lea dless chip carrier ia82510 - plc28i - 01 industrial ia82510 - plc28c - 01 commercial 28 lead plastic leaded chip carrier
ia82510 data sheet asynchronous serial controller as of production ver. 01 copyright ? 2001 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 11 of 11 1 - 888 - 824 - 4184 errata production version 01 1. issue : issuing more than one command via the receive command register (rcm) may result in an unintended lock of the rx fifo. workaround : if multiple commands via the rcm are required, execute them individually. 2. issue : in semi - automatic and automatic transmit mode, rts will assert at the same time as the beginning of the start bit on txd. if rts is used to turn on the txd line driver, the width of the start bit could be distorted. workaround : manual assertion of rts and initiation of the transmit will avoid this issue.

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